1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices capable of storing data for example of a memory circuit and semiconductor memory devices using the same.
2. Description of the Background Art
If a memory circuit such as dynamic random access memory (DRAM) has defect, a semiconductor integrated circuit device with such a memory circuit mounted thereon is not allowed to be shipped as a product. However, producing a defectless product is disadvantageously associated with significantly reduced yield.
Conventionally, such a defect can be replaced by a spare memory cell. More specifically it is typically substituted by a previously arranged memory cell for redundant repair substitution.
More specifically, for a memory circuit with memory cells arranged in an array of rows and columns, a spare plurality of rows and columns are provided and a defective memory cell or line can be substituted with a spare line and thus repaired to increase the yield of defectless chips on a wafer.
This system requires for example that in conducting an in-line test of a wafer any defective addresses be previously programmed and the wafer be then divided into chips and assembled, and thereafter when it is actually used, row and column addresses input be constantly monitored and when a defective address input is detected it be substituted with a spare line.
One such internal circuit generally used is a fuse bank-address detection circuit using laser to cut a polysilicon interconnection, aluminum interconnection and the like, as described for example in IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, October 1983, pp. 441-446.
FIG. 29 is a circuit diagram for illustrating a configuration of a conventional fuse bank-address detection circuit 9000.
Between an internal node n1 and a ground potential is connected a set of a fuse element F11 and a transistor 11 having a gate receiving an internal address signal al and connected in series with fuse element F11. For each of an inverted version of internal address signal al, or an internal address signal /a1, and other internal address signals a2, /a2 to am, /am, there is also provided a respective set of one of similar fuse elements F12-Fm2 and one of similar transistors T12-Tm2.
Internal node n1 is provided with a precharge transistor TP activated by a signal RP to precharge a level of node N1.
In other words, in a decoder of a spare line (hereinafter referred to as a spare decoder) complementary internal addresses are input to the gates of transistors T11-Tm2.
Of fuse elements F11-Fm2, a fuse element corresponding to a defective address is previously cut by laser to program the defective address. When an input address and the programmed, defective address match, an inactivation indicating signal φDA is output to a regular decoder connected to the defective line, to substitute the defective line with a spare line.
Conventional fuse bank-address detection circuit 9000 is disadvantageous as it requires an expensive laser cutter device and the precision in cutting a fuse is also concerned. Such disadvantages are conventionally overcome by an anti-fuse address detection circuit 9100 using an anti-fuse in the form of an electrical fuse.
FIG. 30 is a circuit diagram for illustrating a configuration of such an anti-fuse address detection circuit 9100.
As shown in FIG. 30, anti-fuse address detection circuit 9100 includes an inverter INV110 with an internal node n1 and an input node coupled, an inverter INV120 receiving an output from inverter INV110 in a signal SOUT. Inverter INV120 includes a P channel MOS transistor PQ1 and an N channel MOS transistor NQ1 coupled in series between a power supply potential VCC and a ground potential. Transistors PQ1 and NQ1 have their respective gates both receiving signal SOUT. Inverters INVs110 and 120 together form a latch circuit. An n channel MOS transistor NQ2 is provided between internal nodes N1 and N2 and has a gate receiving power supply potential Vcc.
Furthermore between node N2 and a program signal Vpgm is connected a capacitance element AF1 operating as an anti-fuse element.
Furthermore between node N1 and power supply potential Vcc is provided a P channel MOS transistor PQ3 having a gate receiving a precharge signal PG. Between node N1 and a ground potential is provided an N channel MOS transistor NQ3 having a gate receiving a signal SA.
FIGS. 31-33 are timing plots for illustrating an operation of the FIG. 30 anti-fuse address detection circuit 9100.
Initially with reference to FIG. 31 a fuse blow operation will be described.
At time t1 program signal PG is set low and transistor PQ3 turns on. Thus the latch circuit formed by inverter INV110 and transistors PQ1 and NQ1 is initialized, and node N1 attains a high level.
Then at time t2 program signal PG is set low and signal SA is subsequently set high. Thus, after the latch circuit's node N1 held low, signal SA is set low.
Then at time t3 signal Vpgm is input in a high voltage VCCH. With node N1 having the low level, transistor NQ2 thus turns on and node N2 is driven low.
Between opposite terminals of fuse element AF1 a difference in potential of program potential Vpgm is introduced. Thus, fuse element AF1, receiving a high voltage, would receive high voltage VCCH higher than a breakdown voltage, and thus have breakdown and hence short-circuit.
At time t4 short circuit is introduced, and node N1 gradually goes high. When a logical value of inverter INV110 is exceeded, a level held by the latch circuit is inverted. When the latch circuit is inverted and node N1 goes high, the transistor NQ2 gate attains a potential equal to that of node N1 and transistor NQ2 has a gate-source voltage Vgs of zero volt, and transistor NQ2 turns off. Since transistor NQ2 is shut down, current does not flow to the ground from a node receiving signal Vpgm, after fuse element AF1 has blown.
Herein, inverting a level held by the latch circuit entails a fuse resistance having the same level as the ON resistance of transistor NQ1.
Reference will now be made to FIG. 32 to describe an operation provided when fuse element AF1 is not blown.
At the time t1 signal PG is driven low and the latch circuit is initialized.
At time t2 signal PG is set high to allow the latch circuit to have node N1 held high.
Furthermore at time t3 signal Vpgm is applied in voltage VCCH higher than power supply voltage Vcc.
However, node N1 has the high level and the transistor NQ2 gate receives a high level (the power supply potential VCC level), and transistor NQ2 thus has a source-gate voltage of 0V and it thus has an OFF state. Thus, node N2 applies high voltage Vpgm to transistor NQ2 at the drain and simultaneously rises to potential Vpgm through coupling. Thus also between node N2 and voltage Vpgm a voltage of approximately 0V is attained and the fuse element thus does not break down.
Reference will now be made to FIG. 33 to describe a read operation of anti-fuse address detection circuit 9100.
Initially, signal Vpgm and signal PG are set high (the power supply voltage Vcc level). Then between time t1 and time t2 signal SA is driven high to initialize the latch circuit. In response, node N1 attains a low level.
At time t2 signal SA attains a low level and if a fuse is not blown node N1 is held low.
If a fuse has been blown, the node N1 potential rises from a low level to a potential equal to potential Vpgm since transistor NQ2 conducts and fuse element AF1 is short-circuited, and when the node N1 potential exceeds a logical threshold value of inverter INV110 the latch is inverted and node N1 is held high. These two latch states can be used to program address decision, circuit-tuning, and the like.
As has been described above, in laser-trimming a fuse, a beam of laser is directed to a wire of an LSI still in the form of a wafer to blow the wire and thus program a defective address. If a defect is introduced after packaging, however, the LSI chip of interest in the package cannot receive a beam of laser and it thus cannot be repaired by a laser-trimming fuse (hereinafter referred to as an “LT fuse”). In other words, a semiconductor integrated circuit having been divided into chips and packaged cannot be trimmed if its fuse are adapted to be optically, externally heated and thus cut.
For an electrical fuse, in contrast, stress is applied to a capacitance to program a state, and programming a defective address is thus time-consuming and increases cost relative to time. Furthermore, blowing an electrical fuse requires applying a high voltage. Reliably blowing an electrical fuse requires a high voltage to be applied. However, if the voltage is increased too high, a transistor other than the fuse element receives voltage and a gate which is not subject to destruction may be destroyed. As such, too high a voltage should not be applied.
Thus, for an LT fuse, a beam of laser is used to cut a wire on a wafer to program a defective address. If a defect is introduced after packaging, however, a conventional LT fuse alone cannot repair the defective address.
Furthermore, if an electrical fuse is alone used, stress is applied to a capacitance for destruction, and it is thus time-consuming to program an address to be repaired and it is thus difficult to program it reliably and also in a short period of time.